This invention relates to the field of shift register design, and more particularly to the field of shift register designs employing latches in a more efficient arrangement.
Shift registers are used in many applications in the design of digital circuitry; as delay elements, high speed linear memory, data transfers for programming hardware and extracting diagnostic information, and others.
One of the most common implementations of shift registers is by the use of latches. In the most common latch-based shift registers, each latch's D input is connected to the previous latch's Q output, with the Enable inputs on every other latch connected to opposite phases of the system clock. The data is shifted one latch position per clock phase, with new input data being read at the end of one clock phase and new output data being available at the output on the opposite clock phase. Each pair of adjacent latches in this architecture is structurally equivalent to a Master-Slave flip-flop; so this standard implementation of a shift register is equivalent to one composed of a series of flip-flops.
The disadvantage to this usual approach is that, at any given time, half of the latches are in the track mode and therefore not storing unique data, but rather just duplicating the data stored in the other half of the latches. Thus, 2N latches are required to build an N-bit delay or memory. While this overhead is not too serious for small values of N, for large shift registers the penalty is significant.
Another previously known, but not as common, technique for building shift registers addresses this problem. In this technique, an N-bit shift register is implemented with an N+1 bit dual port RAM and appropriate address counters. One port is used to write a new data bit into the RAM, while the other port is reading the subsequent data bit out of the array. The address counters are incremented every clock cycle, so that on the next cycle a new data entry is written where the previous output had been stored. Although this scheme requires only N+1 storage elements for an N-bit register, it also requires the added complexity of the address counters, read and write amplifiers, etc., and thus is practical only for very large values of N.
What is desired is a technique that allows a compromise between these two methods, each of which is only efficient at one extreme or the other of values of N.